During the use of devices formed of semiconductor materials, overvoltages may appear as a consequence of electrostatic discharge (ESD) phenomena linked to the environment of the devices, especially due to a manipulation by a user.
ESD phenomena are particularly disturbing in the use of devices made in semiconductor substrates on insulators, SOI. SOI substrates are increasingly used since they enable, among other features, decreasing stray capacitances. To protect SOI devices against ESD phenomena, protection means are generally provided at the level of each input/output terminal.
Protection means are, for example, formed of a switch which turns on on occurrence of an ESD discharge on the terminal and then sends the discharge current back to the circuit ground.
The protection switch, for example, is an N-channel MOS transistor having its gate connected to the source. The triggering of the MOS transistor results from the triggering of the parasitic bipolar transistor intrinsic to the MOS transistor.
A disadvantage of such a switch lies in the fact that the substrate typically must have a relatively large thickness. This is an obstacle to the use of such switches in SOI-type processes in which the substrate thickness is limited, often insufficient for a sufficiently sensitive parasitic bipolar transistor to exist. Protection switches formed in solid substrates typically must then be used in an SOI-type process.
FIG. 1 illustrates the equivalent electric diagram of a known protection switch 1 used in thick solid substrates. “Thick substrate” is used to designate a substrate having a thickness greater than the thickness of the silicon-on-insulator layers, which are generally lower than 0.2 μm. Switch 1 comprises two bipolar transistors Q1 and Q2, thyristor-connected, as described hereafter, between two anode and cathode terminals A and K. Anode A is intended to be connected to an input/output terminal IO and cathode K is connected to a reference power supply rail, currently ground (GND). Transistor Q1 is of type PNP and transistor Q2 is of type NPN. Emitter E1 of transistor Q1 forms anode A of the protection means connected to terminal IO. Collector C1 of transistor Q1 is connected to cathode K of the switch via an access resistor R1. Base B1 of transistor Q1 is connected to terminal IO via a resistor R2. Base B1 is also connected to collector C2 of transistor Q2. Emitter E2 of transistor Q2 forms cathode K of the switch intended to be connected to ground GND. Base B2 of transistor Q2 is connected to collector C1.
FIG. 2 is a cross-section view of an embodiment of switch 1 of FIG. 1 in a semiconductor wafer, typically single-crystal silicon. Switch 1 is formed in a surface of the wafer comprising two lightly-doped neighboring regions or wells of complementary types. The N-type well is designated as 20 and the P-type well is designated as 30. Well 20 comprises two N+ and P+ surface regions, respectively 22 and 24 of complementary conductivity types and separated by an insulation region 26. Regions 22 and 24 are connected to a same anode metallization A. Well 30 comprises two heavily-doped N+ and P+ surface regions, respectively 32 and 34, of complementary types separated by an insulation region 36. Regions 32 and 34 are connected to a same cathode metallization K. The four N+, P+, N+, and P+ regions, respectively 22, 24, 32, and 34 are arranged so that two neighboring regions are of complementary conductivity types. P+ region 24 of well 20 and N+ region 32 of well 30 are adjacent, separated by an insulation region 40. Lateral regions 22 and 34 are bounded by a peripheral insulation region 42.
Comparing FIGS. 1 and 2, it is noted that N well 20 forms common point B1/C2 and forms resistor R2 between common point B1/C2 and anode A, and P+ region 24 forms emitter E1. Similarly, P well 30 forms common point C1/B2 and forms resistor R1 interposed between point C1/B2 and cathode K, and N+ region 32 forms emitter E2.
On occurrence of a discharge, a strong current pulse enters anode A of switch 1 and flows towards cathode K through P+ region 24, resistor R2 (well 20), N-P junction 20-30, resistor R1 (well 30), and N+ region 32. There then is a base current injection towards N+ region 22 and into well 30. When the current reaches (or exceeds) the switching threshold of transistors Q1 and Q2, said transistors turn on. The current is then pulled towards ground GND by switch 1.
As illustrated by curve I(V) of FIG. 3, once a given threshold Vi across the nodes A and K (i.e., across the switch 1) is reached, the threshold Vi being set by the characteristics of PN junction 30-20, input resistors R1 and R2, and the current amplification factors of bipolar transistors Q1 and Q2, the voltage across switch 1 collapses, and is thereafter limited, to a value V1. It is noted that this limitation to V1 only occurs after a turn on of the thyristor formed of regions 24, 20, 30, and 32.
A disadvantage of a switch such as the switch 1 lies in its bulk operation. Thus, to form the different regions 22, 24, 32, and 34 bounded by insulation regions 26, 36, 40, and 42 while guaranteeing a sufficient underlying thickness of wells 20 and 30, a relatively thick substrate typically must be available.